As a Principal Engineer Analog Layout at Cyient Semiconductors, a Cyient Group company specializing in high-performance and power-efficient silicon solutions, your role will involve planning and executing the design and layout of high-performance analog and mixed-signal circuits. You will oversee layout verification, ensure physical design constraints are met, and collaborate closely with design teams to optimize performance and layout quality. Additionally, you will be responsible for identifying and resolving technical challenges, mentoring junior team members, and contributing to process improvements.
Key Responsibilities:
• Plan and execute the design and layout of high-performance analog and mixed-signal circuits• Oversee layout verification and ensure physical design constraints are met• Collaborate with design teams to optimize performance and layout quality• Identify and resolve technical challenges in chip design and layout validation processes• Mentor junior team members• Contribute to process improvementsQualifications:
• Proficiency in Analog and Mixed-Signal IC layout, Floor Planning, and placement of circuit elements• Experience with layout tools such as Cadence Virtuoso, Mentor Graphics Calibre, or similar EDA tools• Expertise in DRC (Design Rule Check), LVS (Layout Versus Schematic), and parasitic extraction tools• Ability to handle complex hierarchical layouts and top-level integration in advanced technology nodes• Strong understanding of design constraints, matching, noise reduction techniques, and ESD considerations• Problem-solving skills to analyze and resolve issues in chip design and layout validation processes• Effective communication and collaboration skills for working with cross-disciplinary teams and stakeholders• Bachelors or Masters degree in Electrical Engineering or a related field• 10+ years of experience in full-custom analog layout, with a strong track record of successful tape-outs As a Principal Engineer Analog Layout at Cyient Semiconductors, a Cyient Group company specializing in high-performance and power-efficient silicon solutions, your role will involve planning and executing the design and layout of high-performance analog and mixed-signal circuits. You will oversee layout verification, ensure physical design constraints are met, and collaborate closely with design teams to optimize performance and layout quality. Additionally, you will be responsible for identifying and resolving technical challenges, mentoring junior team members, and contributing to process improvements.Key Responsibilities:
• Plan and execute the design and layout of high-performance analog and mixed-signal circuits• Oversee layout verification and ensure physical design constraints are met• Collaborate with design teams to optimize performance and layout quality• Identify and resolve technical challenges in chip design and layout validation processes• Mentor junior team members• Contribute to process improvementsQualifications:
• Proficiency in Analog and Mixed-Signal IC layout, Floor Planning, and placement of circuit elements• Experience with layout tools such as Cadence Virtuoso, Mentor Graphics Calibre, or similar EDA tools• Expertise in DRC (Design Rule Check), LVS (Layout Versus Schematic), and parasitic extraction tools• Ability to handle complex hierarchical layouts and top-level integration in advanced technology nodes• Strong understanding of design constraints, matching, noise reduction techniques, and ESD considerations• Problem-solving skills to analyze and resolve issues in chip design and layout validation processes• Effective communication and collaboration skills for working with cross-disciplinary teams and stakeholders• Bachelors or Masters degree in Electrical Engineering or a related field• 10+ years of experience in full-custom analog layout, with a strong track record of successful tape-outs